BFG is an open-source full-custom silicon compiler for high-performance FPGA fabrics. BFG makes FPGA IP. It works by hierarchically composing parameterised layout and circuit generators.
Silicon compilers are not novel, but using them for generating FPGAs outside of large companies apparently is.
As an example of what BFG can produce, here is a Configurable Logic Block based around a 4-LUT for Skywater 130nm. It's produced by the LutB generator:
(LutA was full of bad ideas learning.)
It can register either the LUT output or its bypass input. A combinational output pin also lets you select between the LUT output and the bypass, as in:
'
The CLB itself is made up of generators for flip-flops, a hierarchical transmission-gate mux, two different buffer topologies and active 2:1 muxes. Some of these are taken from the open-source sky130_fd_sc_hd library and then parameterised, others were made from scratch.
BFG can then assemble an S-44 LUT based around this CLB and a carry chain. Together with N:1 and N:2 (shared) multiplexer generators for interconnect wiring, and wire buses with configurable break-outs, this is enough to assemble a whole FPGA tile:
The current paradigm for open-source FPGA generation centres on synthesising fabrics from standard cells. Here is the latest comparison of (post parasitic extraction) performance against standard-cell synthesis of the above CLB (all targeting Skywater 130nm):
A 59% reduction in power-delay-area product is, we claim, worth the effort to encode circuit and layout knowledge as code.
Certain classes of process share types of layout rules, which means designs are trivially portable by just changing the values for each of the various rules: minimum spacing, area, width, and so on. As an example of this, the Gf180McuMux uses Sky130Mux code to generate a GF 180 MCU-valid mux, when handed a rulebook with GF 180 MCU values instead. Other clases of process require different layout strategies altogether, and new generators to be written.
BFG works, but has sharp edges. Because it is gradware and I am but one man. Also, even now that we have magical AI, it is bad a lot of the hard parts. Designs are DRC-clean enough to pass LVS, so we can measure their performance and compare it to the popular method of synthesising FPGAs from standard cells.
We think this is how open-source FPGAs should be built, even if it is hard. So we implore you to use, criticise, and contribute to this software!
BFG relies on VLSIR for producing common formats like LEF/DEF, GDS and (the various) Spices.
Once BFG and the prerequisites are installed:
$ cd build
$ ./bfg
--jobs 0 \
--technology ../sky130.technology.pb \
--primitives ../sky130.primitives.pb \
--external_circuits ../sky130hd.pb \
--logtostderr \
--write_text_format \
--run_generator LutB \
--params LutB.params.pb.txt \
--output_library LutB
This will produce LutB.library.pb, a binary-format protocol buffer describing the layout, and LutB.package.pb, a binary-format protocol buffer describing the circuit netlist.
The generator parameter file (LutB.params.pb.txt) is a text-format protocol buffer specifying the options for a particular generator according to the definitions in the parameter proto file.
To get a GDS, you need proto2gds from Layout21:
$ /path/to/Layout21/target/debug/proto2gds --verbose -i /path/to/LutB.library.pb -t /home/arya/src/bfg/sky130.technology.pb -o LutB.gds
To get spice, run simulation/netlist.py:
$ cd simulation
$ ./netlist.py /path/to/LutB.package.pb LutB.sp
See INSTALL.md.
@phdthesis{Reais-Parsi:EECS-2026-283,
Author= {Reais-Parsi, Arya},
Title= {BFG: An Open-Source Silicon Compiler for High-Performance Reconfigurable Fabrics},
School= {EECS Department, University of California, Berkeley},
Year= {2026},
Month= {Aug},
Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2026/EECS-2026-283.html},
Number= {UCB/EECS-2026-283},
Note= {Revised 21 August 2026.},
Abstract= {Synthesisable eFPGA generators have enabled considerable innovation and access to FPGA architecture research in recent years. By generating RTL descriptions of FPGA fabrics, these tools leverage established digital design flows to meaningfully reduce the time taken to tape-out a validated FPGA fabric. Unfortunately, the convenience of employing standard-cells over custom layout comes at the cost of reduced circuit performance. Research architectures lag their commercial counterparts in terms of performance, power and area. At the same time, the end of Moore’s Law and Dennard Scaling is contributing to unprecedented demand for domain-specific accelerators. Performant, easy-to-use and cheaper reconfigurable architectures are needed from the research community to meet this demand. This work presents BFG, an alternative approach to FPGA generation that programmatically generates all circuits together with custom layout. In SkyWater 130 nm, BFG’s cells achieve up to 59% lower power-delay-area product than equivalent logic synthesized with standard cells. In this work we present each of BFG’s four contributions: an unencumbered open-source C++ AMS design framework; a collection of parametric IP generators for FPGA components; a study reverse-engineering a modern commercial architecture; and, a modern columnar fabric architecture together with an example of how BFG might be used to build it. Though our study reveals significant complexity to this approach, we conclude that the performance benefits are justified by the shared development model. BFG provides researchers, enthusiasts and entrepreneurs a repository of fast circuitry and corresponding layout for the development of better FPGA IP.},
}