The RISC-V Virtual Machine
An x86/x64 instruction disassembler written in C
Memory Engine and Scanner for iOS/MacOS using Mach API
RISC-V emulator/simulator in Python
PasRISCV is a RV64GCV/RVA23 RISC-V emulator, which is implemented in Object Pascal
The PasVulkan-based emulator frontend for the PasRISCV RV64GC RISC-V emulator
Custom CPU emulator and assembler
A simulation of a Simple-As-Possible (SAP) computer, implemented in Logisim Evolution.
a web based front end only helper tool that provides Instruction Decoder and Converter in hexadecimal binary decimal form encoding of different ISA
Exhaustive differential validation of all 4.3B AArch64 instruction encodings.
ARMv7-M (Thumb) instruction decoder and disassembler in Python - full instruction set, objdump-compatible output, generated from a YAML spec.
A Java-based MIPS disassembler that converts binary machine code into readable MIPS assembly instructions, supporting key R- and I-format instructions with branch target address resolution.
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